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ai01946 19 a0-a18 ee dq0-dq7 v cc M39432 g ef v ss 8 w r/b figure 1. logic diagram M39432 single chip 4 mbit flash and 256 kbit parallel eeprom memory 3.3v 10% supply voltage for program, erase and read oparations 120ns access time (flash and eeprom blocks) write, program and erase status bits concurrent mode (read flash while writing to eeprom) 100,000 erase/write cycles 10 years data retention low power consumption C stand-by mode: 40 m a C automatic stand-by mode C deep power down mode 64 bytes one time programmable memory standard eprom/otp memory package extended temperature ranges description the M39432 is a memory device combining flash and eeprom into a single chip and using single supply voltage. the memory is mapped in two blocks: 4 mbit of flash memory and 256 kbit of eeprom memory. each space is independant for writing, in concurrent mode the flash memory can be read while the eeprom is being written. a0-a18 address inputs dq0-dq7 data input / outputs ee eeprom block enable ef flash block enable g output enable w write enable r/ b ready/busy output v cc supply voltage v ss ground table 1. signal names tsop40 (nc) 10 x 20 mm october 1998 1/30
symbol parameter value unit t a ambient operating temperature C40 to 85 c t bias temperature under bias C50 to 125 c t stg storage temperature C65 to 150 c v io (2) input or output voltages C0.6 to 7 v v cc supply voltage C0.6 to 7 v v a9 , v g , v ef (2) a9, g, ef voltage C0.6 to 13.5 v notes: 1. except for the rating "operating temperature range", stresses above those listed in the table "absolute maximum ratings" may cause permanent damage to the device. these are stress ratings only and operation of the device at these or any other conditions above those indicated in the operating sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliab ility. refer also to the stmicroelectronics sure program and other relevant quality documents. 2. minimum voltage may undershoot to C2v during transition and for less than 20ns. table 2. absolute maximum ratings (1) an additional 64 bytes of eprom are one time programmable. description (contd) warning: nc = not connected. a3 a0 dq0 a7 nc r/b a4 nc a13 ee a11 nc dq7 a14 nc v ss g dq5 dq1 dq2 dq3 dq4 dq6 a17 w a16 a12 a18 v cc a15 ai01947 M39432 10 1 11 20 21 30 31 40 nc a9 a10 a8 ef a6 a1 a5 a2 nc figure 2. tsop pin connections the M39432 eeprom array may be written by byte or by page of 64 bytes and the integrity of the data can be secured with the help of the software data protection (sdp). the M39432 flash memory array offers 8 blocks of 64 kbytes, each sector may be erased individually, and programmed byte-by-byte. each block can be separately protected and unprotected against pro- gram and erase. block erasure may be suspended, while data is read from other blocks of the flash array (or eeprom memory block), and then re- sumed. the flash array is functionally compatible with the m29w040 4 mbit single voltage flash memory. during a program or erase cycle in the flash array or during a write in the eeprom memory block, the status of the M39432 internal logic can be read on the data outputs dq7,dq6, dq5 and dq3. pin description address inputs (a0-a18). the address inputs for the memory array are latched during a write opera- tion. a0-a14 access locations in the eeprom memory block a0-a18 access locations in the flash memory block. the memory block selected is given by the state on the ee and ef inputs respectively. when a specific voltage (v id ) is applied on the a9 address input, additional specific areas can be accessed: read the manufacturer identifier, read the flash block identifier, read/write the eeprom block identifier, verify the flash block protection status. 2/30 M39432
64k bytes block ai01362b 7ffffh 6ffffh 5ffffh 4ffffh 3ffffh 2ffffh 1ffffh 0ffffh top address 70000h 60000h 50000h 40000h 30000h 20000h 10000h 00000h bottom address a18 1 1 64k bytes block 64k bytes block 64k bytes block 64k bytes block a17 1 1 a16 1 0 1 1 0 0 1 0 0 0 1 1 1 0 001 000 figure 3. flash memory map and block address table data input/output (dq0-dq7). a write operation inputs one byte which is latched when ee (or ef) and write enable w are driven active. data read is valid when one chip enable (chip enable flash or chip enable eeprom) and out- put enable are driven active. the output is high impedance when the chip is deselected (both ee and ef driven high) or the outputs are disabled ( g driven high). read operations are used to output the contents from the memory, the manufacturer identifier, the flash sector protection status, the flash block identifier, the eeprom identifier or the otp row content. memory block enable ( ee and ef). the memory block enable ( ee or ef) activates the memory control logic, input buffers, decoders and sense amplifiers. when the ee input is driven high, the eeprom memory block is not selected; when the ef input is driven high, the flash memory block is not selected. attempts to access both eeprom and flash blocks ( ee low and ef low) are forbid- den. switching between the two memory block enables ( ee and ef) must not be made on the same clock cycle, a delay of greater than t ehfl must be inserted. the M39432 is in standby when both ef and ee are high (when no internal erase or programming is running). the power consumption is reduced to the standby level and the outputs are in the high impedance state, independent of the output en- able g or write enable w inputs. after 150ns of inactivity and when the addresses are driven at cmos levels, the chip automatically enters a pseudo standby mode where consumption is reduced to the cmos standby value, while the outputs continue to drive the bus. output enable ( g). the output enable gates the outputs through the data buffers during a read operation. the data outputs are in the high imped- ance state when the output enable g is high. during sector protect and sector unprotect opera- tions, the g input must be forced to v id level (12v + 0.5v) (for flash memory block only). write enable ( w). addresses are latched on the falling edge of w, and data inputs are latched on the rising edge of w. ready/busy (r/ b). the ready/busy pin outputs the status of the device when the eeprom mem- ory block is under the write condition Cr/ b = 0: internal writing is in process, Cr/ b = 1: no internal writing in in process. it should be noted that the ready/busy pin does not reflect the status of programming/erasing in the flash memory. this status bit can be used when reading (or fetch- ing opcodes) in the flash memory block. the ready/busy output uses an open drain tran- sistor, allowing therefore the use of the M39432 in multi-memory applications with all ready/busy out- puts connected to a single ready/busy line (or- wired with an external pull-up resistor). 3/30 M39432
operation ef ee g w dq0 - dq7 read v il v ih v il v ih read in flash block v ih v il v il v ih read in eeprom block write v il v ih v ih v il write in flash block v ih v il v ih v il write in eeprom block output disable v il v ih v ih xhi-z v ih v il v ih xhi-z standby v ih v ih xx hi-z note: x = v il or v ih . table 3. basic operations operations the M39432 memory is addressed through 19 inputs a0-a18 and provides data on eight data inputs/outputs dq0-dq7 with the help of four con- trol lines: chip enable eeprom ( ee), chip enable flash ( ef), output enable ( e) and write enable ( w) inputs. an operation is defined as the basic decoding of the logic level applied to the control input pins ( ef, ee, g, w) and the specified voltages applied on the relevant address pins. these operations are detailed in table 3. read. both chip enable and output enable (that is ef and g or ee and g) must be low in order to read the output of the memory. read operations are used to output the contents from the flash or eeprom block, the manufac- turer identifier, the flash sector protection status, the flash block identifier, the eeprom identifier or the otp row content. notes: C the chip enable input mainly provides power control and should be used for device selection. the output enable input should be used to gate data onto the output in combination with active ef or ee input signals. C the data read depends on the previous instruc- tion entered into the memory (see table 4). write. a write operation can be used for two goals: C either write data in the eeprom memory block C or enter a sequence of bytes composing an instruction. the reader should note that programming a flash byte is an instruction (see instructions paragraph). writing data requires: C the chip enable (either ee or ef) to be low C the write enable ( w) to be low with output enable (g) high. addresses in flash block (or eeprom block) are latched on the falling edge of w or ef ( ee) which- ever occurs last; the data to be written in flash block (eeprom block) is latched on the rising edge of w or ef ( ee) whichever occurs first. specific read and write operations. device specific data is accessed through operations de- coding the v id level applied on a9 (v id = 12v + 0.5v) and the logic levels applied on address inputs (a0, a1, a6). these specific operations are: C read the manufacturer identifier C read the device identifier C define the flash sector protection C read the eeprom identifier C write the eeprom identifier note: the otp row (64 bytes) is accessed with a specific software sequence detailed in the para- graph "write in otp row". instructions an instruction is defined as a sequence of specific write operations. each received byte is sequen- tially decoded (and not executed as standard write operations) and the instruction is executed when the correct number of bytes are properly received and the time between two consecutive bytes is shorter than the time-out value. the sequencing of any instruction must be followed exactly, any invalid combination of instruction bytes or time-out between two consecutive bytes will reset the device logic into a read memory state (when addressing the flash block) or directly de- coded as a single operation when addressing the eeprom block. 4/30 M39432
instruction ee ef cycle 1 cycle 2 cycle 3 cycle 4 cycle 5 cycle 6 cycle 7 read manufacturer identifier (2) 10 aah @5555h 55h @2aaah 90h @5555h read identifier with (a0,a1,a6) at (0,0,0) read flash identifier (2) 10 aah @5555h 55h @2aaah 90h @5555h read identifier with (a0,a1,a6) at (1,0,0) read otp row 0 1 aah @5555h 55h @2aaah 90h @5555h read byte 1 read byte 2 read byte n read block protection status (2) 10 aah @5555h 55h @2aaah 90h @5555h read identifier with (a0,a1,a6) at (0,1,0) program a flash byte 1 0 aah @5555h 55h @2aaah a0h @5555h data @address erase one flash block 10 aah @5555h 55h @2aaah 80h @5555h aah @5555h 55h @2aaah 30h @sector address 30h @sector address (3) erase the whole flash 1 0 aah @5555h 55h @2aaah 80h @5555h aah @5555h 55h @2aaah 10h @5555h suspend block erase 1 0 b0h @any address resume block erase 1 0 30h @any address eeprom power down 01 aah @5555h 55h @2aaah 30h @5555h deep power down 1 0 20h @5555h sdp enable (eeprom) 01 aah @5555h 55h @2aaah a0h @5555h write byte 1 write byte 2 write byte n sdp disable (eeprom) 01 aah @5555h 55h @2aaah 80h @5555h aah @5555h 55h @2aaah 20h @5555h write in otp row 0 1 aah @5555h 55h @2aaah b0h @5555h write byte 1 write byte 2 write byte n return (from otp read or eeprom power down) 01 f0h @ any address reset 1 0 aah @5555h 55h @2aaah f0h @any address reset (short instruction) 10 f0h @any address notes: 1. aah @5555h means write byte aah at address 5555h. 2. this instruction can also be performed as a simple read operation with a9=v id (refer to read chapter). 3. additional blocks to be erased must be entered within 80 m s. table 4. instructions (1) 5/30 M39432
the M39432 set of instructions includes: C program a byte in the flash block C read a flash sector protection status C erase instructions: flash sector erase, flash block erase, flash sector erase suspend, flash sector erase resume C eeprom power down C deep power down C set/reset the eeprom software write protec- tion (sdp) C otp row access C reset and return C read identifiers: read the manufacturer identi- fier, read the flash block identifier these instructions are detailed in table 4. for efficient decoding of the instruction, the two first bytes of an instruction are the coded cycles and are followed by a command byte or a confirmation byte. the coded cycles consist of writing the data aah at address 5555h during the first cycle and data 55h at address 2aaah during the second cycle. in the specific case of the erase instruction, the instruction expects confirmation by two additional coded cycles. power supply and current consump- tion eeprom power down. the M39432 can be set with the eeprom in power down with the help of the eeprom power down instruction (see table 4). once the eeprom power down instruction is decoded, the eeprom block cannot be accessed unless a further return instruction is decoded. deep power down. the M39432 can be set in the lowest i cc consumption mode with the help of the deep power down instruction (see table 4). once the instruction is decoded, the device is set in a sleep mode until a reset instruction is decoded. power up. the M39432 internal logic is reset upon a power-up condition to read memory status. any write operation in eeprom is inhibited during the first 5 ms following the power-up. either ef, ee or w must be tied to v ih during power-up for the maximum security of the data contents and to remove the possibility of a byte being written on the first rising edge of ef, ee or w. any write cycle initiation is locked when vcc is below v lko . read read operations and instructions can be used to: C read the contents of the memory array (flash block and eeprom block) C read the memory array (flash block and eeprom block) status and identifiers. read data (flash and eeprom blocks) both chip enable ef (or ee) and output enable ( g) must be low in order to read the data from the memory. read the manufacturer identifier the manufacturers identifier can be read with two methods: a read operation or a read instruction. read operation. the manufacturers identifier can be read with a read operation with specific logic levels applied on a0, a1, a6 and the v id level (v id = 12v + 0.5v) on a9 (see table 5). read instruction. the manufacturers identifier can also be read with a single instruction composed of 4 operations: 3 specific write operations (see table 4) and a read which outputs the manufac- turer identifier, the flash block identifier or the flash sector protection status (depending on the levels applied on a0, a1, a6, a16, a17 and a18. identifier ef ee g w a0a1a6a9 other addresses dq0 - dq7 read the manufacturer identifier v il v ih v il v ih v il v il v il v id dont care 20h read the flash block identifier v il v ih v il v ih v ih v il v il v id dont care 0e3h read the eeprom block identifier v ih v il v il v ih xxv il v id dont care 64 bytes user defined note: x = dont care. table 5. device identifiers 6/30 M39432
read the flash block identifier the flash block identifier can be read with two methods: a read operation or a read instruction. read operation. the flash block identifier (e3h) can be read with a single read operation with specific logic levels applied on a0, a1, a6 and the v id level on a9 (see table 5). read instruction. the flash block identifier can also be read with an instruction composed of 4 operations: 3 specific write operations and a read (see table 4). read the eeprom block identifier the eeprom block identifier (64 bytes, user de- fined) can be read with a single read operation with a6 = 0 and a9 = v id (see table 5). read the otp row the otp row is mapped in the eeprom block ( ee = 0, ef = 1). read of the otp row (64 bytes) is by an instruction (see table 4) composed of three specific write operations of data bytes at three specific memory locations (each location in a dif- ferent page) before reading the otp row content. when accessing the otp row, only the lsb ad- dresses (a6 to a0) are decoded where a6 must be 0. each read of the otp row has to be followed by the return instruction (see table 4). read the flash sector protection status reading the flash sector protection status is by an instruction similar to the read manufacturer iden- tifier instruction, the only difference being the value of the logic levels applied on a0, a1, a6, while a16, a17 and a18 define the flash sector whose protec- tion has to be verified. such a read instruction will output a 01h if the flash sector is protected and a 00h if the flash sector is not protected. the flash sector protection status can also be verified with a read operation (see chapter: flash block specific features), with v id on a9. read the status bits the M39432 provides several write operation status flags which may be used to minimize the application write (or erase or program) time. these signals are available on the i/o port bits when programming (or erasing) are in progress. it should be noted that the ready/busy pin also reflects the status of the eeprom write (the ready/busy pin does not reflect the status of the flash program- ming/erasing). data polling flag, dq7. when erasing or pro- gramming into the flash block (or when writing into the eeprom block), bit dq7 outputs the comple- ment of the bit being entered for program- ming/writing on dq7. once the program instruction or the write operation is performed, the true logic value is read on dq7 (in a read opera- tion). flash memory block specific features: C data polling is effective after the fourth w pulse (for programming) or after the sixth w pulse (for erase). it must be performed at the address being programmed or at an address within the flash sector being erased. C during an erase instruction, dq7 outputs a 0. after completion of the instruction, dq7 will out- put the last bit programmed (that is a 1 after erasing). C if the byte to be programmed is in a protected flash sector, the instruction is ignored. C if all the flash sectors to be erased are pro- tected, dq7 will be set to 0 for about 100 m s, and then return to the previous addressed byte. no erasure will be performed. C if all sectors are protected, a bulk erase instruc- tion is ignored. toggle flag, dq6. the M39432 also offers another way for determining when the eeprom write or the flash memory program instruction is com- pleted. during the internal write operation, the dq6 will toggle from 0 to 1 and 1 to 0 on subsequent attempts to read any byte of the memory, when either g , ee or ef is low. when the internal cycle is completed the toggling will stop and the data read on dq0-dq7 is the addressed memory byte. the device is now acces- sible for a new read or write operation. the opera- tion is completed when two successive reads yield the same output data. ef ee dq7 dq6 dq5 dq4 dq3 dq2 dq1 dq0 flash v il v ih data polling toggle flag error flag x erase time-out xxx eeprom v ih v il data polling toggle flag xx x xxx note: x = not guaranteed value, can be read either 1 or 0. table 6. status bit 7/30 M39432
flash memory block specific features: a. the toggle bit is effective after the fourth w pulse (for programming) or after the sixth w pulse (for erase). b. if the byte to be programmed belongs to a pro- tected flash sector, the instruction is ignored and: C if all the flash sectors selected for erasure are protected, dq6 will toggle to 0 for about 100 m s, and then return to the previous ad- dressed byte. C if all sectors are protected, the bulk erase in- struction is ignored. error flag, dq5 (flash block only). this bit is set to 1 when there is a failure during either a flash byte programming or a sector erase or the bulk erase. in case of error in flash sector erase or byte program, the flash sector in which the error oc- curred or to which the programmed byte belongs, must not be used any longer (other flash sectors may still be used). the error bit resets after reset instruction. during a correct program or erase, the error bit will set to 0. erase time-out flag, dq3 (flash block only). the erase timer bit reflects the time-out period allowed between two consecutive sector erase instructions. the erase timer bit is set to 0 after a sector erase instruction for a time period of 100 m s 20% unless an additional sector erase instruction is decoded. after this time period or when the additional sector erase instruction is decoded, dq3 is set to 1. write a byte (or a page) in eeprom it should be noticed that writing in the eeprom block is an operation, it is not an instruction (as for programming a byte in the flash block). write a byte in eeprom block a write operation is initiated when chip enable ee is low and write enable w is low with output enable g high. addresses are latched on the falling edge of w, ee whichever occurs last. once initiated, the write operation is internally timed until completion, that is during a time t w . the status of the write operation can be found by reading the data polling and toggle bits (as de- tailed in the read chapter) or the ready/busy output. this ready/busy output is driven low from the write of the byte being written until the comple- tion of the internal write sequence. ai01698b write aah in address 5555h write 55h in address 2aaah write a0h in address 5555h sdp is set write aah in address 5555h write 55h in address 2aaah write a0h in address 5555h write data to be written in any address sdp enable algorithm page write instruction page write instruction write is enabled sdp set sdp not set write in memory write data + sdp set after twc figure 4. eeprom sdp enable flowcharts 8/30 M39432
write a page in eeprom block the page write allows up to 64 bytes within the same eeprom page to be consecutively latched into the memory prior to initiating a programming cycle. all bytes must be located in a single page address, that is a6-a14 must be the same for all bytes. once initiated, the page write operation is internally timed until completion, that is during a time t wc . the status of the write operation can be seen by reading the data polling and toggle bits (as de- tailed in the read chapter) or the ready/busy output. this ready/busy output is driven low from the write of the first byte to be written until the completion of the internal write sequence. a page write is composed of successive write instructions which must be sequenced within a time period (between two consecutive write operations) that is smaller than the t wlwl value. if this period of time exceeds the t wlwl value, the internal program- ming cycle will start. eeprom block software data protection a protection instruction allows the user to inhibit all write modes to the eeprom block: the software data protection (referenced as sdp in the follow- ing). the sdp feature is useful for protecting the eeprom memory from inadvertent write cycles that may occur during uncontrolled bus conditions. the M39432 is shipped as standard in the unpro- tected state meaning that the eeprom memory contents can be changed by the user. after the sdp enable instruction, the device enters the protect mode where no further write operations have any effect on the eeprom memory contents. the device remains in this mode until a valid sdp disable instruction is received whereby the device reverts to the unprotected state. to enable the software data protection, the device has to be written (with a page write) with three specific data bytes at three specific memory loca- tions (each location in a different page) as shown in figure 4. this sequence provides an unlock key to enable the write action, and, at the same time, sdp continues to be set. any further write in eeprom when the sdp is set will use this same sequence of three specific data bytes at three specific memory locations followed by the bytes to write. the first sdp enable sequence can be di- rectly followed by the bytes to written. similarly, to disable the software data protection the user has to write specific data bytes into six different locations with a page write addressing different bytes in different pages, as shown in fig- ure 5. the software data protection state is non-volatile and is not changed by power on/off sequences. the sdp enable/disable instructions set/reset an inter- nal non-volatile bit and therefore will require a write time t wc , this write operation can be monitored only on the toggle bit (status bit dq6) and the ready/busy pin. the ready/busy output is driven low from the first byte to be written (that is the first write aah, @5555h of the sdp set/reset se- quence) until the completion of the internal write sequence. ai01699b write aah in address 5555h write 55h in address 2aaah write 80h in address 5555h unprotected state after twc (write cycle time) write aah in address 5555h write 55h in address 2aaah write 20h in address 5555h page write instruction figure 5. sdp disable flowchart ef ee g wa6a9 other addresses dq0 - dq7 v ih v il v ih v il v il v id dont care 64 bytes user defined table 7. write the eeprom block identifier 9/30 M39432
write otp row writing (only one time) in the otp row (64 bytes) is enabled by an instruction. this instruction is composed of three specific write operations of data bytes at three specific memory locations (each location in a different page) followed by the the data to store in the otp row (refer to table 4). when accessing the otp row, the only lsb ad- dresses (a6 to a0) are decoded, with a6 = 0. write the eeprom block identifier the eeprom block identifier can be written with a single write operation with specific logic levels applied on a6 and the v id level on a9 (see table 7). program in the flash block it should be noted that writing data into the eeprom block and the flash block is not per- formed in a similar way: the flash memory requires an instruction (see instruction chapter) for erasing and another instruction for programming one (or more) byte(s), the eeprom memory is directly written with a simple operation (see operation chapter). program instuction. during the execution of the program instruction, the flash block memory will not accept any further instructions. the flash block memory can be programmed byte- by-byte. the program instruction is a sequence of three specific write operations followed by writing the address and data byte to be programmed into the flash block memory (see table 4). the M39432 automatically starts and performs the programming after the fourth write operation. during programming, the memory status may be checked by reading the status bits dq5, dq6 and dq7, as detailed in the following sections. read dq5 & dq7 at valid address start read dq7 fail pass ai01369 dq7 = data yes no yes no dq5 = 1 dq7 = data yes no figure 6. data polling flowchart read dq5 & dq6 start read dq6 fail pass ai01370 dq6 = toggle no no yes yes dq5 = 1 no yes dq6 = toggle figure 7. data toggle flowchart 10/30 M39432
data polling. polling on dq7 is a method of check- ing whether a program or an erase instruction is in progress or completed (see figure 6). when a program instruction is in progress, data bit dq7 is the complement of the original data bit 7; when dq7 is identical to the old data and the error bit dq5 is still 0, the instruction is complete. to de- termine if dq7 is valid, each poll must store the original data for comparison, and if they are the same, it can be considered that the operation was successful. the error bit dq5 is checked to ensure timing limits have not exceeded. when an erase operation is in progress, dq7 is always 0, and will be 1 when finished, so long as dq5= 0. in all cases, when dq5 is 1, dq7 should be checked again, in case dq7 changed simultane- ously with dq5. if dq7 = true data (program) or dq7 = 1 (erase), the operation is successful and execution should return to the caller. a suggested second read will provide all true data (program) or all ffh (erase). otherwise, this should be flagged as an error, and the device should be reset. data toggle. checking the toggle bit dq6 is an alternative method of checking if program or erase operations are in progress or completed (see fig- ure 7). when an operation is in progress, data bit dq6 constantly toggles for successive read opera- tions. when dq6 no longer toggles and the error bit dq5 is 0, the operation is completed. to deter- mine if dq6 has toggled, each polling action re- quires 2 consecutive read operations of the data, and if the data read is the same, it can be consid- ered that the operation was successful. the error bit dq5 is checked to ensure timing limits have not been exceeded. in all cases, when dq5 is 1, dq6 should be checked again, in case dq6 has changed simultaneously with dq5. if dq6 has stopped toggling, the operation is successful and execution should return to the caller. a suggested second read will provide all true data (program) or all ffh (erase). otherwise, this event should be flagged as an error, and the device should be reset. erase in the flash block it should be noted that: a. programming any byte of one flash sector (or bulk) requires that the flash sector (or bulk) has been previously erased (once for all bytes within the sector or bulk) with the correct instruction (see instructions chapter). b. writing in the eeprom memory is an operation triggering an automatic sequencing of byte erase followed by a byte write. writing in eeprom does not require a specific erase operation before writ- ing. bulk erase instruction. the bulk erase instruc- tion uses six write operations followed by read operations of the status register bits, as described in table 4. if any byte of the bulk erase instruction is wrong, the bulk erase instruction aborts and the device is reset to the read flash memory status. during a bulk erase, the memory status may checked by reading the status bits dq5, dq6 and dq7, as detailed in the "program in the flash block" chapter. the error bit (dq5) returns a 1 if there has been an erase failure (maximum num- ber of erase cycles have been executed). it is not necessary to program the array with 00h, the M39432 will automatically do this before eras- ing to ffh. during the execution of the bulk erase instruction, the flash block logic does not accept any instruc- tion. sector erase in flash block. the sector erase instruction uses six write operations, as described in table 4. additional flash sector erase confirm commands and flash sector addresses can written subsequently to erase other flash sectors in par- allel, without further coded cycles, if the additional instruction is transmited in a shorter time than the timeout period to end of period. the input of a new sector erase instruction will restart the time-out period. the status of the internal timer can be monitored through the level of dq3 (erase time-out bit), if dq3 is 0 the sector erase instruction has been re- ceived and the timeout is counting; if dq3 is 1, the timeout has expired and the M39432 is erasing the flash sector(s). before and during erase timeout, any instruction different than erase suspend and erase resume will abort the instruction and reset the device to read array mode. it is not necessary to program the flash sector with 00h as the M39432 will do this automatically before erasing (byte = ffh). during a sector erase, the memory status may be checked by reading the status bits dq5, dq6 and dq7, as detailed in the "program instruction" chap- ter. during the execution of the erase instruction, the flash block logic accepts only the reset and erase suspend instructions (erasure of one flash sector may be suspended, in order to read data from another flash sector, and then resumed). 11/30 M39432
ef ee g w a0 a1 a6 a9 a12 a16 a17 a18 dq0 - dq7 v il v ih v id v il xxxv id x sa sa sa protection activation v il v ih v il v ih v il v ih v il v id xsasasa verify the protection status: when dq0= 1, the block is protected notes: x = dont care. sa = software address. table 8. flash sector protection ef ee g w a0 a1 a6 a9 a12 a16 a17 a18 dq0 - dq7 v id v ih v id v il xxxv id v ih v ih xx activation of unprotected mode v il v ih v il v ih v il v ih v ih v id x sasasa verify the protection status: when 00h, the block is unprotected notes: x = dont care. sa = software address. table 9. flash unprotection erase suspend instruction. when a flash sector erase operation is in progress, the erase suspend instruction may suspend the operation by writing b0h at any address (see table 4). this allows reading of data from another flash sector while erase is in progress. erase suspend is accepted only during the flash sector erase instruction exe- cution and defaults to read array mode. an erase suspend instruction entered during an erase timeout will, in addition to suspending the erase, terminates the timeout. the toggle bit dq6 stops toggling when the M39432 internal logic is suspended. the toggle bit status must be monitored at an address out of the flash sector being erased. toggle bit will stop toggling between 0.1 m s and 15 m s after the erase suspend instruction has been written. the M39432 will then automatically be set into read flash block memory array mode. when erase is suspended, reading from flash sectors being erased will output invalid data, a read from flash sector not being erased is valid. during an erase suspend, the flash memory will respond only to erase resume and reset instruc- tions. a reset instruction will definitively abort erasure and can leave invalid data in the flash sectors being erased. erase resume instruction. if an erase suspend instruction was previously executed, the erase op- eration may be resumed by this instruction. the erase resume instruction consists of writing 30h at any address (see table 4). flash block specific features flash sector protection. each flash sector can be separately protected against program or erase. flash sector protection provides additional data security, as it disables all program or erase opera- tions. this mode is activated when both a9 and g are set to v id (12v + 0.5v) and the flash sector address is applied on a16, a17 and a18, as shown in figure 8 and table 8. flash sector protection is programmed with the help of a specific sequence of levels applied on ef, ee, g, a0, a1, a6, a9, a16, a17 and a18; this sequence includes a verification of the protection status on dq0 as shown in table 8. any attempt to program or erase a protected flash sector will be ignored by the device. remarks: C the verify operation is a read with a simulated worst case conditions. this allows a guarantee of the retention of the protection status C during the application life, the sector protection status can be accessed with a regular read instruction without applying a "high voltage" v id on a9. this instruction is detailed in table 4. flash sector unprotection. flash sectors can be unprotected to allow updating of their contents. note that the sector unprotection unprotects all sectors (sector 0 up to sector 7). flash sector unprotection is activated with a spe- cific sequence of levels applied on ef, ee, g, a0, a1, a6, a9, a12, a16, a17 and a18; this sequence includes a verification of the protection status on dq0-dq7 as shown in figure 9 and table 9. 12/30 M39432
block address on a16, a17, a18 ee = v ih ai01948b g, a9 = v id , ef = v il n = 0 wait 4s wait 100s w = v il w = v ih g = v ih read dq0 at protection address: a0, a6 = v il , a1 = v ih and a16, a17, a18 defining block a9 = v ih ++n = 25 start fail pass yes no dq0 = 1 yes no a9 = v ih wait 4s figure 8. block protection flowchart 13/30 M39432
ai01949b a6, a12, a16 = v ih g, a9 = v ih data ef, g, a9 = v id wait 4s w = v ih ef, g = v ih read at unprotection address: a1, a6 = v ih , a0 = v il and a16, a17, a18 defining block (see note 1) wait 10ms wait 4s = 00h increment block n = 0 wait 4s w = v il ++n = 1000 start fail yes yes no pass no last sect. yes no ee = ef = v ih figure 9. block unprotecting flowchart note: 1. a6 is kept at v ih during unprotection algorithm in order to secure best unprotection verification. during all other protection status reads, a6 must be kept at v il . 14/30 M39432
this allows a guarantee of the retention of the protection status. remarks: C the verify operation is a read with a simulated worst case conditions. this allows a guarantee of the retention of the protection status C during the application life, the sector protection status can be accessed with a regular read instruction without "high voltage" v id on a9. this instruction is detailed in table 4. reset instruction. the reset instruction resets the device internal logic in a few m s. reset is an instruction of either one write operation or three write operations (refer to table 4). supply rails. normal precautions must be taken for supply voltage decoupling, each device in a system should have the v cc rail decoupled with a 0.1 m f capacitor close to the v cc and v ss pins. the printed circuit board trace width should be sufficient to carry the v cc program and erase currents re- quired. glossary block: eeprom block (256 kbit) or flash block (4mbit) bulk: the whole flash block (4mbit) sector: 64 kbyte of flash memory page: 64 bytes of eeprom write and program: writing (into the eeprom block) and programming (the flash block) is not performed in a similar way: C the flash memory requires an instruction (see instruction chapter) for erasing and another in- struction for programming one (or more) byte(s) C the eeprom memory is directly written with a simple operation (see operation chapter). sdp: software data protection. used for protect- ing the eeprom block against false write opera- tions (as in noisy environments). ai01950 1.5v 2.4v 0.45v figure 10. ac testing input output waveform ai01951 v cc c l = 100pf c l includes jig capacitance v out = 1.5v when the device under test is in the hi-z output state. 1n914 device under test 1n914 i ol i oh figure 11. output ac testing load circuit symbol parameter test condition min max unit c in input capacitance v in = 0v 6 pf c out output capacitance v out = 0v 12 pf note: 1. sampled only, not 100% tested. table 11. capacitance (1) (t a = 25 c, f = 1 mhz ) input rise and fall times 10ns input pulse voltages 0.45v to 2.4v input timing ref. voltages 0.8v and 2v output timing ref. voltages 1.5v table 10. ac measurement conditions flash block specific features (cont d) 15/30 M39432
symbol parameter test condition min max unit i li input leakage current 0v v in v cc 1 m a i lo output leakage current 0v v out v cc 1 m a i cc1 (1) supply current (read flash) ttl ee = v ih , ef = v il , g = v ih , f = 6mhz 15 ma i cc2 supply current (read eeprom) ttl ee = v il , ef = v ih , g = v ih , f = 6mhz 15 ma i cc3 supply current (standby) cmos ef = ee = v cc 0.2v 40 m a i cc4 supply current (flash block program or erase) byte program, sector or chip erase in progress 20 ma i cc5 supply current (eeprom write) during t wc 20 ma i cc6 supply current in deep power down mode after a deep power down instruction (see table 4) 2 m a v il input low voltage C0.5 0.8 v v ih input high voltage 2 v cc + 0.5 v v ol output low voltage i ol = 2ma 0.45 v v oh output high voltage i oh = C100 m av cc C0.4 v i oh = C2ma 0.85 v cc v v id a9 high voltage 11.5 12.5 v i id v id current a9 = v id 50 m a v lko v cc minimum for write, erase and program 1.9 2.2 v note: 1. when reading the flash block when an eeprom byte(s) is under a write cycle, the supply current is i cc1 + i cc5 . table 12. dc characteristics (t a = 0 to 70 c or C40 to 85 c; v cc = 3.3v 10%) 16/30 M39432
ai01952 tavav tavqv taxqx telqx tehqz tehqx tglqv tglqx tghqx tghqz valid a0-a18 ee (ef) g dq0-dq7 telqv valid address valid and chip enable output enable data valid tehfl tehfl ef (ee) figure 12. read mode ac waveforms note: write enable ( w) = high 17/30 M39432
symbol alt parameter test condition M39432 unit -120 -150 min max min max t avav t rc address valid to next address valid (ee, ef) = (v il , v ih ) or (ee, ef) = (v ih , v il ), g = v il 120 150 ns t avqv t acc address valid to output valid (ee, ef) = (v il , v ih ) or (ee, ef) = (v ih , v il ), g = v il 120 150 ns t elqx (1) t lz chip enable low to output transition g = v il 00ns t elqv (2) t ce chip enable low to output valid g = v il 120 150 ns t glqx (1) t olz output enable low to output transition (ee, ef) = (v il , v ih ) or (ee, ef) = (v ih , v il ) 00ns t glqv (2) t oe output enable low to output valid (ee, ef) = (v il , v ih ) or (ee, ef) = (v ih , v il ) 55 55 ns t ehqx t oh chip enable high to output transition g = v il 00ns t ehqz (1) t hz chip enable high to output hi-z g = v il 40 40 ns t ghqx t oh output enable high to output transition (ee, ef) = (v il , v ih ) or (ee, ef) = (v ih , v il ) 00ns t ghqz (1) t df output enable high to output hi-z (ee, ef) = (v il , v ih ) or (ee, ef) = (v ih , v il ) 40 40 ns t axqx t oh address transition to output transition (ee, ef) = (v il , v ih ) or (ee, ef) = (v ih , v il ), g = v il 00ns t ehfl t ced ee ( ef) active to ef ( ee) 100 100 ns notes: 1. sampled only, not 100% tested. 2. g may be delayed by up to t elqv - t glqv after the falling edge of ee (or ef) without increasing t elqv . table 13a. read ac characteristics (t a = 0 to 70 c or C40 to 85 c; v cc = 3.3v 0.3v) 18/30 M39432
symbol alt parameter test condition M39432 unit -200 -250 min max min max t avav t rc address valid to next address valid (ee, ef) = (v il , v ih ) or (ee, ef) = (v ih , v il ), g = v il 200 250 ns t avqv t acc address valid to output valid (ee, ef) = (v il , v ih ) or (ee, ef) = (v ih , v il ), g = v il 200 250 ns t elqx (1) t lz chip enable low to output transition g = v il 00ns t elqv (2) t ce chip enable low to output valid g = v il 200 250 ns t glqx (1) t olz output enable low to output transition (ee, ef) = (v il , v ih ) or (ee, ef) = (v ih , v il ) 00ns t glqv (2) t oe output enable low to output valid (ee, ef) = (v il , v ih ) or (ee, ef) = (v ih , v il ) 70 120 ns t ehqx t oh chip enable high to output transition g = v il 00ns t ehqz (1) t hz chip enable high to output hi-z g = v il 50 60 ns t ghqx t oh output enable high to output transition (ee, ef) = (v il , v ih ) or (ee, ef) = (v ih , v il ) 00ns t ghqz (1) t df output enable high to output hi-z (ee, ef) = (v il , v ih ) or (ee, ef) = (v ih , v il ) 50 60 ns t axqx t oh address transition to output transition (ee, ef) = (v il , v ih ) or (ee, ef) = (v ih , v il ), g = v il 00ns t ehfl t ced ee ( ef) active to ef ( ee) 100 100 ns notes: 1. sampled only, not 100% tested. 2. g may be delayed by up to t elqv - t glqv after the falling edge of ee (or ef) without increasing t elqv . table 13b. read ac characteristics (t a = 0 to 70 c or C40 to 85 c; v cc = 3.3v 0.3v) 19/30 M39432
ai01953 e (1) g w a0-a18 dq0-dq7 valid valid v cc tvchel twheh twhwl telwl tavwl twhgl twlax twhdx write cycle tdvwh twlwh tghwl rb twhrl twhrh figure 13. write ac waveforms, w controlled notes: address are latched on the falling edge of w, data is latched on the rising edge of w. e is either ef when ee = v ih or ee when ef = v ih . 20/30 M39432
e (1) ai01954 g w a0-a18 dq0-dq7 valid valid v cc tvchwl tehwh tehel twlel tavel tehgl telax tehdx write cycle tdveh teleh tghel dq0-dq7 rb twhrl figure 14. write ac waveforms, e controlled notes: address are latched on the falling edge of e, data is latched on the rising edge of e. e is either ef when ee = v ih or ee when ef = v ih . 21/30 M39432
symbol alt parameter M39432 unit -120 -150 -200 -250 min max min max min max min max t avav t wc address valid to next address valid 120 150 200 150 ns t elwl (2) t cs chip enable low to write enable low 0000 ns t wlwh t wp write enable low to write enable high 50 65 80 50 ns t dvwh t ds input valid to write enable high 50 65 80 50 ns t whdx t dh write enable high to input transition 0000 ns t wheh (2) t ch write enable high to chip enable high 0000 ns t whwl t wph write enable high to write enable low 30 35 35 20 ns t avwl t as address valid to write enable low 0000 ns t wlax t ah write enable low to address transition 50 65 65 50 ns t ghwl output enable high to write enable low 0000 ns t vchel t vcs v cc high to chip enable low 50 50 50 50 m s t whqv1 (1) write enable high to output valid (program) 15 15 15 10 m s t whqv2 (1) write enable high to output valid (sector erase) 2.0302.0302.0301.030 sec t whwl0 time out between 2 consecutive section erase 80 80 80 80 m s t whgl t oeh write enable high to output enable low 0000 ns t whrl (3) t db write enable high to ready/busy output low 150 150 150 150 ns notes: 1. time is measured to data polling or toggle bit, t whqv = t whq7v + t q7vqv 2. chip enable means (ee, ef) = (v il , v ih ) or (ee, ef) = (v ih , v il ). 3. with a 3.3k w pull-up resistor. table 14. write ac characteristics, write enable controlled (t a = 0 to 70 c or C40 to 85 c; v cc = 3.3v 0.3v) 22/30 M39432
symbol alt parameter M39432 unit -120 -150 -200 -250 min max min max min max min max t wlwl t blc byte load cycle (eeprom) 0.2 150 0.2 150 0.2 150 0.2 150 m s t whrh t wc write cycle time (eeprom) 10 10 10 10 ms t avav address valid to next address valid 120 150 200 150 ns t wlel t ws write enable low to memory block enable low 0000 ns t eleh t cp memory block enable low to memory block enable high 50 65 80 50 ns t dveh t ds input valid to memory block enable high 50 65 80 50 ns t ehdx t dh memory block enable high to input transition 0000 ns t ehwh t wh memory block enable high to write enable high 0000 ns t ehel t cph memory block enable high to memory block enable low 30 35 35 20 ns t avel t as address valid to memory block enable low 0000 ns t elax t ah memory block enable low to address transition 50 65 65 50 ns t ghel output enable high to memory block enable low 0000 ns t vchwl t vcs v cc high to write enable low 50 50 50 50 m s t ehqv1 (1) memory block enable high to output valid (program) 15 15 15 10 m s t ehqv2 (1) memory block enable high to output valid (sector erase) 2.0 30 2.0 30 2.0 30 1.0 30 sec t ehgl t oeh memory block enable high to output enable low 0000 ns t ehrl (2) t db eeprom block enable high to ready/busy output low 150 150 150 150 ns notes: 1. time is measured to data polling or toggle bit, t whqv = t whq7v + t q7vqv . 2. with a 3.3k w pull-up resistor. table 15. write ac characteristics, ee or ef controlled (t a = 0 to 70 c or C40 to 85 c; v cc = 3.3v 0.3v) 23/30 M39432
ai01955b e (5) g w a0-a18 dq7 ignore valid dq0-dq6 byte address (within blocks) data output valid tavqv tehq7v tglqv twhq7v valid tq7vqv dq7 data polling (last) cycle data verify read cycle data polling read cycles last cycle of program or erase telqv figure 15. data polling dq7 ac waveforms notes: 1. all other timings are as a normal read cycle. 2. dq7 and dq0-dq6 can transmit to valid at any point during the data output valid period. 3. t whq7v is the program or erase time. 4. during erasing operation byte address must be within blocks being erased. 5. e is either ef when ee = v ih or ee when ef = v ih . 24/30 M39432
symbol alt parameter M39432 unit -120 -150 -200 -250 min max min max min max min max t whq7v1 (2) write enable high to dq7 valid (program, w controlled) 10 10 10 10 m s t whq7v2 (2) write enable high to dq7 valid (sector erase, w controlled) 1.5 30 1.5 30 1.5 30 1.5 30 sec t ehq7v1 (2) flash block enable high to dq7 valid (program, ef controlled) 10 10 10 10 m s t ehq7v2 (2) flash block enable high to dq7 valid (sector erase, ef controlled) 1.5 30 1.5 30 1.5 30 1.5 30 sec t q7vqv q7 valid to output valid (data polling) 50 55 70 55 ns t whqv1 write enable high to output valid (program) 10 10 10 10 m s t whqv2 write enable high to output valid (sector erase) 1.5 30 1.5 30 1.5 30 1.5 30 sec t ehqv1 flash block enable high to output valid (program) 10 10 10 10 m s t ehqv2 flash block enable high to output valid (sector erase) 1.5 30 1.5 30 1.5 30 1.5 30 sec notes: 1. all other timings are defined in read ac characteristics table. 2. t whq7v is the program or erase time. table 16. data polling and toggle bit ac characteristics (1) (t a = 0 to 70 c or C40 to 85 c; v cc = 3.3v 0.3v) parameter M39432 unit min typ max chip program (byte) 8 sec chip erase (preprogrammed) 3 30 sec chip erase 10 sec sector erase (preprogrammed) 1 30 sec sector erase 2 sec byte program 10 1200 m s program/erase cycles (per sector) 100,000 cycles table 17. program, erase times and program, erase endurance cycles (flash block) (t a = 0 to 70 c or C40 to 85 c; v cc = 3.3v 0.3v) 25/30 M39432
ai01956 e (2) g w a0-a18 dq6 dq0-dq5, tavqv stop toggle last cycle of program of erase valid valid valid ignore dq7 data toggle read cycle read cycle twhqv tehqv telqv tglqv data toggle read cycle figure 16. data toggle dq6 ac waveforms notes: 1. all other timings are as a normal read cycle. 2. e is either ef when ee = v ih or ee when ef = v ih . 26/30 M39432
ai02028 a0-a14 e g dq0-dq7 w twlwl addr 0 rb addr 1 addr 2 addr n twhrh twlwh twhwl twhrl byte 0 byte 1 byte 2 byte n figure 17. eeprom page write mode ac waveforms, w controlled 27/30 M39432
ordering information scheme devices are shipped from the factory with the memory content set at all "1s" (ffh). for a list of available options (speed, package, etc...) or for further information on any aspect of this device, please contact the stmicroelectronics sales office nearest to you. speed -12 120ns -15 150ns -20 200ns -25 250ns operating voltage v 3.0v to 3.6v package nc tsop40 10 x 20mm temp. range 1 0 to 70 c 5 C20 to 85 c 6 C40 to 85 c option t tape & reel packing example: M39432 -15 v nc 1 t 28/30 M39432
tsop-a d1 e 1 n cp b e a2 a n/2 d die c l a1 a symb mm inches typ min max typ min max a 1.20 0.047 a1 0.05 0.15 0.002 0.006 a2 0.95 1.05 0.037 0.041 b 0.17 0.27 0.007 0.011 c 0.10 0.21 0.004 0.008 d 19.80 20.20 0.780 0.795 d1 18.30 18.50 0.720 0.728 e 9.90 10.10 0.390 0.398 e0.50C C0.020C C l 0.50 0.70 0.020 0.028 a 05 05 n40 40 cp 0.10 0.004 drawing is not to scale. tsop40 - 40 lead plastic thin small outline, 10 x 20mm 29/30 M39432
information furnished is believed to be accurate and reliable. however, stmicroelectronics assumes no responsib ility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of stmicroelectronics. specifications mentioned in this publicati on are subject to change without notice. this publication supersedes and replaces all information previously supplied. stmicroelectronics product s are not authorized for use as critical components in life support devices or systems without express written approval of stmicroelectro nics. the st logo is a registered trademark of stmicroelectronics ? 1998 stmicroelectronics - all rights reserved stmicroelectronics group of companies australia - brazil - canada - china - france - germany - italy - japan - korea - malaysia - malta - mexico - morocco - the neth erlands - singapore - spain - sweden - switzerland - taiwan - thailand - united kingdom - u.s.a. http://www.st.com 30/30 M39432

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